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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
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Advance Information
256KB and 512KB Synchronous Fast Static RAM Module
The MCM36F6 (256KB) is configured as 64K x 36 bits and the MCM36F7 (512KB) is configured as 128K x 36 bits. Both are packaged in a 144-pin dual- in-line memory module (DIMM). Each module uses Motorola's 3.3 V 64K x 18 bit flow-through BurstRAMs. Address (A), data inputs (DQ, DP), and all control signals except output enable (G) are clock (K) controlled through positive-edge-triggered noninverting registers. Write cycles are internally self-timed and initiated by the rising edge of the clock (K) input. This feature provides increased timing flexibility for incoming signals. Synchronous byte write (BWx) and global byte write (WE) allows writes to either individual bytes or to both bytes. * * * * * * * * Single 3.3 V + 10%, - 5% Power Supply Plug and Pin Compatibility with 1MB and 2MB Multiple Clock Pins for Reduced Loading All Inputs and Outputs are LVTTL Compatible Byte Write and Global Write Capability Fast SRAM Access Times: 10 ns Berg Connector, Part Number: 61178-31844 144-Pin DIMM Module
MCM36F6 MCM36F7
144-LEAD DIMM CASE 1154-01 TOP VIEW 143
61 59
1
This document contains information on a new product. Specifications and information herein are subject to change without notice.
2/10/98
(c) Motorola, Inc. 1998 MOTOROLA FAST SRAM
MCM36F6*MCM36F7 1
MCM36F6 BLOCK DIAGRAM
E0 G0 A0 - A15 ADSP BW0 BW1 K0 64K x 18 SE1 G A0 - A15 ADSC SBa SBb K SE2 ADV ADSP SGW SW LBO SE3 DQa0 - DQa7 DQa8 DQb0 - DQb7 DQb8 64K x 18 SE1 G A0 - A15 ADSC SBa SBb K SE2 ADV ADSP SGW SW LBO SE3 DQa0 - DQa7 DQa8 DQb0 - DQb7 DQb8
PD1 = GND PD0 = NC
BW2 BW3 K1
VDD WE
VSS
DQ0 - DQ7 DP0 DQ8 - DQ15 DP1
DQ16 - DQ23 DP2 DQ24 - DQ31 DP3
MCM36F6*MCM36F7 2
MOTOROLA FAST SRAM
MCM36F7 BLOCK DIAGRAM
64K x 18 K SE1 G A0 - A15 ADSC SBa SBb SGW DQa0 - DQa7 DQa8 DQb0 - DQb7 DQb8 SE2 ADV ADSP SW LBO SE3 64K x 18 K SE1 G A0 - A15 ADSC SBa SBb SGW DQa0 - DQa7 DQa8 DQb0 - DQb7 DQb8 SE2 ADV ADSP SW LBO SE3 PD1 = NC PD0 = GND
K0 E0 G0 A0 - A15 ADSP BW0 BW1 WE
K1
BW2 BW3
VDD
VSS
DQ0 - DQ7 DP0 DQ8 - DQ15 DP1
DQ16 - DQ23 DP2 DQ24 - DQ31 DP3
VDD
VSS K2 E1 G1
64K x 18 A0 - A15 ADSC SBa SBb SGW DQb8 DQb0 - DQb7 DQa8 DQa0 - DQa7 SE2 ADV ADSP SW LBO SE3 K SE1 G
K3
64K x 18 A0 - A15 ADSC SBa SBb SGW DQb8 DQb0 - DQb7 DQa8 DQa0 - DQa7 SE2 ADV ADSP SW LBO SE3 K SE1 G
MOTOROLA FAST SRAM
MCM36F6*MCM36F7 3
PIN ASSIGNMENT 144-LEAD DIMM TOP VIEW
VSS A0 A2 A4 VDD NC NC VSS A6 A8 A10 NC VDD A12 A14 NC VSS PD0 VSS BW0 E0 VSS K1 VSS DQ0 VDD DQ2 DQ4 DQ6 VSS VDD DQ8 DQ10 VSS DQ12 DQ14 DP0 NC NC VSS WE NC VDD NC NC NC VDD NC NC NC VSS BW2 E1 VDD DQ16 DQ18 NC NC NC VSS K3 VSS DQ20 VSS DQ22 DQ24 DQ26 DQ28 VDD DQ30 DP2 VSS
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144
VSS A1 A3 A5 VDD NC NC VSS A7 A9 A11 NC VDD A13 A15 NC VSS PD1 VSS BW1 G0 VSS K0 VSS DQ1 VDD DQ3 DQ5 DQ7 VSS VDD DQ9 DQ11 VSS DQ13 DQ15 DP1 NC NC VSS ADSP NC VDD NC NC NC VDD NC NC NC VSS BW3 G1 VDD DQ17 DQ19 NC NC NC VSS K2 VSS DQ21 VSS DQ23 DQ25 DQ27 DQ29 VDD DQ31 DP3 VSS
MCM36F6*MCM36F7 4
MOTOROLA FAST SRAM
PIN DESCRIPTIONS
Pin Locations 3, 4, 5, 6, 7, 8, 17, 18, 19, 20, 21, 22, 27, 28, 29, 30, 82 39, 40, 103, 104 73, 74, 141, 142 (a) 49, 50, 53, 54, 55, 56, 57, 58, (b) 63, 64, 65, 66, 69, 70, 71, 72 (c) 109, 110, 111, 112, 125, 126, 129, 130 (d) 131, 132, 133, 134, 135, 136, 139, 140 41, 105 42, 106 46, 45, 122, 121 35, 36 81 Symbol A0 - A15 ADSP BW0 - BW3 DP0 - DP3 DQ0 - DQ31 I/O Type Input Input Input Description Synchronous Address Inputs: These inputs are registered and must meet setup and hold times. Synchronous Addresss Status Controller: Initiates read, write, or chip deselect cycle. Synchronous Byte Write Inputs: x refers to the byte being written (byte a, b, c, d). WE overrides BWx. Synchronous Parity Data Inputs/Outputs. Synchronous Data Inputs/Outputs.
E0, E1 G0, G1 K0 - K3 PD0, PD1 WE
Input Input Input Output Input
Synchronous Chip Enable: Active low to enable chip. Negated high -- deselects chip when ADSP is asserted. Asynchronous Output Enable Input. Clock: This signal registers the address, data in, and all control signals except G. Presence Detect Bits. Synchronous Global Write: This signal writes all bytes regardless of the status of the BWx signals. If only byte write signals SBx are being used, tie this pin high. Power Supply: 3.3 V + 10%, - 5%.
9, 10, 25, 26, 51, 52, 61, 62, 85, 86, 93, 94, 107, 108, 137, 138 1, 2, 15, 16, 33, 34, 37, 38, 43, 44, 47, 48, 59, 60, 67, 68, 79, 80, 101, 102, 119, 120, 123, 124, 127, 128, 143, 144 11, 12, 13, 14, 23, 24, 31, 32, 75, 76, 77, 78, 83, 84, 87, 88, 89, 90, 91, 92, 95, 96, 97, 98, 99, 100, 113, 114, 115, 116, 117, 118
VDD
Supply
VSS
Supply
Ground.
NC
--
No Connection: There is no connection to the chip.
MOTOROLA FAST SRAM
MCM36F6*MCM36F7 5
TRUTH TABLE (See Notes 1 through 4)
Next Cycle Deselect Begin Read Read Read Begin Write Write Address Used None External Current Current External Current Ex 1 0 X X 0 X ADSP 0 0 1 1 0 1 Gx X 0 1 0 X X DQx High-Z DQ High-Z DQ High-Z High-Z WRITE2, 4 X Read Read Read Write Write
NOTES: 1. X = don't care, 1 = logic high, 0 = logic low. 2. Write is defined as either any BWx or WE low. 3. Gx is an asynchronous signal and is not sampled by the clock K. Gx drives the bus immediately (tGLQX) following Gx going low. 4. On write cycles that follow read cycles, Gx must be negated prior to the start of the write cycle to ensure proper write data setup times. Gx must also remain negated at the completion of the write cycle to ensure proper write data hold times.
ABSOLUTE MAXIMUM RATINGS (Voltages Referenced to VSS = 0 V)
Rating Power Supply Voltage Voltage Relative to VSS Output Current (per I/O) Ambient Temperature Die Temperature Temperature Under Bias Storage Temperature Symbol VDD Vin, Vout Iout TA TJ Tbias Tstg Value - 0.5 to + 4.6 - 0.5 to VDD + 0.5 20 0 to 70 110 - 10 to + 85 - 55 to + 125 Unit V V mA C C C C This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high-impedance circuit. This BiCMOS memory circuit has been designed to meet the dc and ac specifications shown in the tables, after thermal equilibrium has been established. This device contains circuitry that will ensure the output devices are in High-Z at power up.
NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for extended periods of time could affect device reliability.
MCM36F6*MCM36F7 6
MOTOROLA FAST SRAM
DC OPERATING CONDITIONS AND CHARACTERISTICS
(VDD = 3.3 V + 10%, - 5%, TA = 0 to 70C, Unless Otherwise Noted) RECOMMENDED OPERATING CONDITIONS (Voltages Referenced to VSS = 0 V)
Parameter Supply Voltage Input High Voltage Input Low Voltage * VIL - 2.0 V for t tKHKH/2. Symbol VDD VIH VIL Min 3.135 2.0 - 0.5* Typ 3.3 -- -- Max 3.6 VDD + 0.3 0.8 Unit V V V
DC CHARACTERISTICS
Parameter Input Leakage Current (0 V Vin VDD) Output Leakage Current (0 V Vin VDD) Output Low Voltage (IOL = + 8.0 mA) Output High Voltage (IOH = - 4.0 mA) Symbol Ilkg(I) Ilkg(O) VOL VOH Min -- -- -- 2.4 Max 1.0 1.0 0.4 -- Unit A A V V
POWER SUPPLY CURRENTS
Parameter AC Supply Current (Device Selected, All Outputs Open, Cycle Time tKHKH min) MCM36F6DG10 MCM36F7DG10 Symbol IDDA ISB1 Min -- -- Max 430 630 200 400 70 140 Unit mA mA Notes 1, 2, 3
CMOS Standby Supply Current (Deselected, MCM36F6DG10 Clock (K) Cycle Time tKHKH, All Inputs Toggling MCM36F7DG10 at CMOS Levels Vin VSS + 0.2 V or VDD - 0.2 V) Clock Running Supply Current (Deselected, Clock (K) Cycle Time tKHKH, All Other Inputs Held to Static CMOS Levels Vin VSS + 0.2 V or VDD - 0.2 V) MCM36F6DG10 MCM36F7DG10
ISB2
--
mA
4
NOTES: 1. Reference AC Operating Conditions and Characteristics for input and timing (VIH/VIL, tr/tf, pulse level 0 to 3.0 V, VIH = 3.0 V). 2. All addresses transition simultaneously low (LSB) and then high (HSB). 3. Data states are all zero. 4. Device in deselected mode as defined by the Truth Table.
MCM36F6 CAPACITANCE (f = 1.0 MHz, dV = 3.0 V, TA = 0 to 70C, Periodically Sampled Rather Than 100% Tested)
Parameter Input Capacitance I/O Capacitance BWx, K Other Inputs Symbol Cin CI/O Typ -- -- -- Max 11 17 14 Unit pF pF
MCM36F7 CAPACITANCE (f = 1.0 MHz, dV = 3.0 V, TA = 0 to 70 C, Periodically Sampled Rather Than 100% Tested)
Parameter Input Capacitance K Addr, ADSP, WE Other Inputs Symbol Cin Typ -- -- -- -- Max 11 29 17 23 Unit pF
I/O Capacitance
CI/O
pF
MOTOROLA FAST SRAM
MCM36F6*MCM36F7 7
AC OPERATING CONDITIONS AND CHARACTERISTICS
(VDD = 3.3 V + 10%, - 5%, TA = 0 to 70C, Unless Otherwise Noted)
Input Timing Measurement Reference Level . . . . . . . . . . . . . . . 1.5 V Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 3.0 V Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . . 1 V/ns (20 to 80%) Output Timing Reference Level . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 V Output Load . . . . . . . . . . . . . . See Figure 1 Unless Otherwise Noted
DATA RAM READ/WRITE CYCLE TIMING (See Notes 1, 2, 3, and 4)
MCM36F6 - 10 MCM36F7 - 10 Parameter P Cycle Time Clock Access Time Output Enable to Output Valid Clock High to Output Active Clock High to Output Change Output Enable to Output Active Output Disable to Q High-Z Clock High to Q High-Z Clock High Pulse Width Clock Low Pulse Width Setup Times: Address ADSP Data In Write Chip Enable Address ADSP, ADSC, ADV Data In Write Chip Enable Symbol S bl tKHKH tKHQV tGLQV tKHQX1 tKHQX2 tGLQX tGHQZ tKHQZ tKHKL tKLKH tAVKH tADKH tDVKH tWVKH tEVKH tKHAX tKHADX tKHDX tKHWX tKHEX Min 15 -- -- 0 3 0 -- 3 5 5 2.5 Max -- 10 5 -- -- -- 5 5 -- -- -- Unit Ui ns ns ns ns ns ns ns ns ns ns ns 5 5 5 5, 6 5, 6 Notes N
Hold Times:
0.5
--
ns
NOTES: 1. Write is defined as either any BWx and SW low or WE is low. 2. Chip Enable is defined as E0 low, SE2 high, and SE3 low whenever ADSP or ADSC is asserted. 3. All read and write cycle timings are referenced from K0 or G0. 4. G0 is a don't care after write cycle begins. To prevent bus contention, G0 should be negated prior to start of write cycle. 5. This parameter is sampled and not 100% tested. 6. Measured at 200 mV from steady state.
TIMING LIMITS
Z0 = 50 OUTPUT 50 VL = 1.5 V The table of timing values shows either a minimum or a maximum limit for each parameter. Input requirements are specified from the external system point of view. Thus, address setup time is shown as a minimum since the system must supply at least that much time (even though most devices do not require it). On the other hand, responses from the memory are specified from the device point of view. Thus, the access time is shown as a maximum since the device never provides data later than that time.
Figure 1. AC Test Load
MCM36F6*MCM36F7 8
MOTOROLA FAST SRAM
READ/WRITE CYCLES
t KHKH K t KHKL t KLKH
Ax
A
B
C
D
E
F
G
ADSP
Ex
BW
Gx t KHQV DQx t KHQZ DESELECTED Q(n) Q(A) t KHQX1 READ WRITES Q(B) t KHQX2 Q(C) t GHQZ D(D) D(E) D(F) t GLQX READ t GLQV Q(G)
ORDERING INFORMATION
(Order by Full Part Number) MCM
Motorola Memory Prefix Part Number
36F
X
XX
XX
Speed (10 = 10 ns) Package (DG = Gold Pad DIMM) Memory Size (6 = 256KB, 7 = 512KB)
Full Part Numbers -- MCM36F6DG10
MCM36F7DG10
MOTOROLA FAST SRAM
MCM36F6*MCM36F7 9
PACKAGE DIMENSIONS
144-LEAD DIMM CASE 1154-01 67.75 67.45 0.1 M A B C 63.6 4.8 24.5
(DATUM C) 2X R
C L
OF MODULE
A 3
MIN
3.8
MAX
25.55 25.25
6 B
2X
(3.3)
2X
(3.7)
PIN 2
PIN 144 2X
COMPONENT AREA (BACK)
4.1 3.9 0.1
4.2
M
MIN
CBA
FULL R
(DATUM C)
2X 2 MIN
2.7 2.4
0.25
MAX
0.1 0.5
L L
0.65 0.55 A BC A VIEW C
0.8
NOTES: 1. DIMENSIONING AND TOLERANCING CONFORM TO ASME Y14.5M, 1994. 2. ALL DIMENSIONS ARE IN mm. 3. CARD THICKNESS APPLIES ACROSS TABS AND INCLUDES PLATING AND/OR METALIZATION.
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MCM36F6*MCM36F7 10
EEEE EEEE
EEEEEEEEEEEEEE EEEEEEEEEEEEEE EEEEEEEEEEEEEE EEEEEEEEEEEEEE EEEEEEEEEEEEEE
COMPONENT AREA (FRONT) PIN 1
20 3.2 A
2X MIN
5
MAX
4.6
VIEW B
PIN 143
23.2 23.2
32.8 32.8
1.95 1.65 0.15 0.1
M
1.1 0.9
M
OPTIONAL HOLES
A VIEW A-A
CBA
4.6 2.1
VIEW C
FULL R
4
MIN
(DATUM C)
EEEEEEEEEEEEEE EEEEEEEEEEEEEE EEEEEEEEEEEEEE EEEEEEEEEEEEEE EEEEEEEEEEEEEE EEEEEEEEEEEEEE
4.1 3.9 2.5
1.6 1.4
C VIEW B
MCM36F6/D MOTOROLA FAST SRAM

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